Conventionally, a memory of a multi-block configuration that suppresses an increase in size by sharing a readout circuit and a write circuit between two memory cell arrays has been sometimes adopted. As the memory cell arrays for use in the memory of the multi-block configuration, a random accessible nonvolatile memory, for example, a NOR type flash memory may be adopted.
In the flash memory, for example, a state where an electric charge is accumulated in a floating gate (FG) of a memory cell is set as a logical value “0”, and a state where no electric charge is accumulated is set as a logical value “1”. In order to perform writing to respective memory cells, electric charges need to be removed from the FGs temporarily, and erasure to initialize the respective memory cells to “1” is performed by applying a high voltage to erase gates (EG) of the respective memory cells. At the time of writing, injection of electric charges is not performed (hereinafter, referred to as unprogramming) in order to keep the memory cells at the logical value “1”, or electric charges are injected to the FGs to change the respective memory cells from the logical value “1” to “0” (hereinafter, referred to as programming).
However, in a nonvolatile memory, a relatively long time period is required for programming. Consequently, the nonvolatile memory has a problem that a test time period becomes long, and test cost increases.